FPGA Reaction Timer
Summary
Programmed a reaction timer on a Nexys-4 DDR FPGA using VHDL. Implemented a finite state machine, arithmetic logic unit, pseudo-random generator, and 7-segment display interface.
Programmed a reaction timer on a Nexys-4 DDR FPGA using VHDL. Implemented a finite state machine, arithmetic logic unit, pseudo-random generator, and 7-segment display interface.